
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:14:42 03/18/2011
-- Design Name:   interfaz
-- Module Name:   C:/Xilinx92i/interfaz_cyclone/tb_interfaz.vhd
-- Project Name:  interfaz_cyclone
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: interfaz
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE work.Definitions.ALL;

ENTITY tb_interfaz_vhd IS
END tb_interfaz_vhd;

ARCHITECTURE behavior OF tb_interfaz_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT interfaz
	PORT(
		PC : IN std_logic_vector(9 downto 0);
		clk_i : IN std_logic;
		proc_state : IN processor_state;
		instr_ack_i : IN std_logic;
		instr_word_i : IN std_logic_vector(17 downto 0);
		data_ack_i : IN std_logic;
		data_word_i : IN std_logic_vector(7 downto 0);
		port_ack_i : IN std_logic;
		port_word_i : IN std_logic_vector(7 downto 0);
		pc_out : IN std_logic_vector(9 downto 0);
		clr_i : IN std_logic;          
		instr_cyc_o : OUT std_logic;
		instr_stb_o : OUT std_logic;
		instr_addr_o : OUT std_logic_vector(9 downto 0);
		data_cyc_o : OUT std_logic;
		data_stb_o : OUT std_logic;
		data_we_o : OUT std_logic;
		data_addr_o : OUT std_logic_vector(7 downto 0);
		data_word_o : OUT std_logic_vector(7 downto 0);
		port_cyc_o : OUT std_logic;
		por_stb_o : OUT std_logic;
		port_we_o : OUT std_logic;
		port_addr_o : OUT std_logic_vector(7 downto 0);
		port_word_o : OUT std_logic_vector(7 downto 0);
		ir : OUT std_logic_vector(17 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_i :  std_logic := '0';
	SIGNAL proc_state :  processor_state := mem;
	SIGNAL instr_ack_i :  std_logic := '0';
	SIGNAL data_ack_i :  std_logic := '0';
	SIGNAL port_ack_i :  std_logic := '0';
	SIGNAL clr_i :  std_logic := '0';
	SIGNAL PC :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL instr_word_i :  std_logic_vector(17 downto 0) := (others=>'0');
	SIGNAL data_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL port_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL pc_out :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL instr_cyc_o :  std_logic;
	SIGNAL instr_stb_o :  std_logic;
	SIGNAL instr_addr_o :  std_logic_vector(9 downto 0);
	SIGNAL data_cyc_o :  std_logic;
	SIGNAL data_stb_o :  std_logic;
	SIGNAL data_we_o :  std_logic;
	SIGNAL data_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL data_word_o :  std_logic_vector(7 downto 0);
	SIGNAL port_cyc_o :  std_logic;
	SIGNAL por_stb_o :  std_logic;
	SIGNAL port_we_o :  std_logic;
	SIGNAL port_addr_o :  std_logic_vector(7 downto 0);
	SIGNAL port_word_o :  std_logic_vector(7 downto 0);
	SIGNAL ir :  std_logic_vector(17 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: interfaz PORT MAP(
		PC => PC,
		clk_i => clk_i,
		proc_state => proc_state,
		instr_cyc_o => instr_cyc_o,
		instr_stb_o => instr_stb_o,
		instr_ack_i => instr_ack_i,
		instr_addr_o => instr_addr_o,
		instr_word_i => instr_word_i,
		data_cyc_o => data_cyc_o,
		data_stb_o => data_stb_o,
		data_we_o => data_we_o,
		data_ack_i => data_ack_i,
		data_addr_o => data_addr_o,
		data_word_o => data_word_o,
		data_word_i => data_word_i,
		port_cyc_o => port_cyc_o,
		por_stb_o => por_stb_o,
		port_we_o => port_we_o,
		port_ack_i => port_ack_i,
		port_addr_o => port_addr_o,
		port_word_o => port_word_o,
		port_word_i => port_word_i,
		ir => ir,
		pc_out => pc_out,
		clr_i => clr_i
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		
		wait for 100 ns;
		proc_state<=fetch;
		pc<="0000000001";
		
		
		wait for 100 ns;
		instr_ack_i<='1';
		instr_word_i<="101100011100110101";
		

		wait; -- will wait forever
	END PROCESS;

END;
